1. Field of the Invention
The present invention relates to a processor and a processing method of the same.
2. Description of the Related Art
FIG. 3 is a diagram showing a configuration example of a processor. An instruction prefetch buffer 302 prefetches an instruction code from an instruction cache memory 301 to store the instruction code. Stages S1 to S5 constitute an instruction pipeline and sequentially pipeline-process the instruction codes stored in the instruction prefetch buffer 302. For instance, the instruction code stored in the instruction prefetch buffer 302 is decoded in the stage S1, then is executed in the stage S2, and then is written back in the stage S3. An instruction code I1 and an address A1 thereof are stored in the stage S1, an instruction code I2 and an address A2 thereof are stored in the stage S2, an instruction code I3 and an address A3 thereof are stored in the stage S3, an instruction code I4 and an address A4 thereof are stored in the stage S4, and an instruction code I5 and an address A5 thereof are stored in the stage S5.
An instruction address AA is an address to be sent to the stage S5 next. An arithmetic logic unit (ALU) 304 adds an instruction address AA and an offset address AS to output the instruction address AA for the next time. In a case where an instruction code is a 4-byte instruction, the offset address AS is “+4”. By adding +4 to the instruction address AA each time, the instruction codes can be executed in address order.
An exception control unit 303 performs exception handling under interrupt control in such cases when an inexecutable instruction is executed. At this time, a current instruction address is temporarily saved and the saved instruction address is restored after the exception handling is finished, and then the processing before the interruption is resumed.
Japanese Patent Application Laid-open No. 2003-228483 describes a microprocessor in which a co-processor control unit intercepts address outputting from a CPU to a cache memory so that an address is not supplied to the cache memory when an execution address is outputted from the CPU to the co-processor.
Every time an instruction is to be executed, the above-described processor reads an instruction code from the cache memory 301 or a main memory. For instance, a processor operating at 1 GHz needs to access the memory more than 1 billion times, and accordingly, a ratio of power consumption of the instruction cache memory 301 has reached several tens % of the total power consumption of the processor. This problem is serious especially in a processor that executes a plurality of instructions simultaneously by using recent technologies such as superscalar or VLIW.